The invention relates to data process systems and, more particularly, to data processing systems employing multiple busses.
In computers and data processing systems, a bus is commonly employed to interconnect the various elements of the system. For example, a central processing unit is typically connected to memory components, input/output (1/O) devices, etc. via a bus capable of carrying the signals associated with the operation of each element. These signals include, for example, data signals, clock signals, and other control signals. The bus must be capable of carrying such signals to all components coupled to the bus so that the desired operation can be carried out by the computer system.
As computer systems achieve increasingly higher levels of performance, it is sometimes desirable to provide more than one bus in the computer system. For example, it may be desired to provide a high speed main system bus which interconnects processors and high speed memory components, and to provide a separate bus which interconnects 1/O devices such as disc drives and tape drives to an I/O controller.
The separate busses in a multibus computer system must be interconnected, which introduces complexities into the system. One method for interconnecting busses is to provide a bus interconnect adapter consisting of first and second adapter modules each connected to one of the busses, and an interconnect bus connecting the two adapter modules. When data is to be transferred from one bus to the other, a transaction is initiated on the one bus, according to a predetermined set of rules, commonly called a protocol. The adapter module connected to the bus on which the transaction is initiated obtains control of the interconnect bus, typically by issuing a "request" signal over the interconnect bus. The other adapter module, if it is not already in control of the interconnect bus, will respond with a "grant" signal. The initiating adapter module gains control of the interconnect bus and begins to generate the signals which constitute the data transfer transaction. This "request/grant" solution is acceptable in many applications, but can result in a limitation on the speed at which data can be transferred between the busses.
In some multibus computer systems, the busses operate with different cycle times. This introduces additional complexity into the problem of transferring data between busses. Such complexity arises because major events on a bus occur in synchronism with clock signals which control the cycle time of the bus, such as a change of state of either the main clock signal or a multiphase clock signal derived from the main clock signal. When data is to be transferred between busses having different cycle times, it is necessary to insure that a control signal generated by circuitry connected to one of the busses will be recognized and acted upon by circuitry connected to the other bus.
In synchronizing transactions between two busses having different cycle times, the transmission of signals from the slow bus to the fast bus is relatively straightforward. That is, a control signal operated in accordance with the cycle time of the slow bus will remain in its asserted state over at least one complete cycle of the faster bus, thus ensuring that the signal in its asserted condition is captured and recognized by the faster bus.
Transmitting a signal from the fast bus to the slow bus, however, is more difficult. This is because a signal which is asserted only for the duration of one bus cycle on the fast bus may return to its deasserted condition before the clock on the slow bus transitions from one state to another. Since incoming control signals will only be synchronized, that is, recognized, upon the occurrence of a change of state in a clock signal on the slow bus, it is possible for a control signal of finite duration generated by the fast bus to fail to be recognized by the slow bus.
Various techniques are known for addressing this problem. For example, a control signal generated by the fast bus can be passed through a multistage counter circuit, prior to sending it to the slow bus, to "stretch" the assertion time of the control signal over a period of several fast bus clock cycles, the stretched control signal having an assertion time greater than the cycle time of the slow bus. This method has the disadvantage of requiring relatively complex logic to generate the control signals, a particularly undesirable characteristic where many control signals must be generated. Moreover, if the assertion time of the control signal is only marginally longer than the cycle time of the slow bus, circuitry associated with the slow bus may have only one chance to detect the control signal before it returns to its deasserted condition. If noise is present on the system, noise may prevent the slow bus from recognizing the single change of state of the control signal, thus resulting in lower system reliability.
Another known method of transmitting control signals from a fast bus to a slow bus is to utilize the incoming control signal on the slow bus side to control the clock terminal of synchronizing circuitry, thus resulting in an edge-triggered control signal receiving circuit. A control signal generated by the fast bus having a duration equal to the cycle time of the fast bus will, if all goes well, result in receipt of the control signal on the slow bus side. As with the "stretch" method described above, however, the slow bus circuitry may have only one chance to detect the incoming control signal before it returns to its deasserted condition, rendering the system susceptible to noise. Moreover, an incoming control signal having a clean edge is needed to accurately operate edge-triggered receiving circuitry. Thus, systems employing edge-triggered circuitry require careful attention to design to insure good electrical integrity of the generated signals. Such critical design requirements increase the cost of the system.
Thus, none of the known methods of transmitting control signals from a fast bus to a slow bus in a multibus computer system are completely satisfactory.